FuriosaAI and Broadcom Co-Develop 2nm AI Chips

Seoul, South Korea - FuriosaAI has signed a partnership with Broadcom to jointly develop a third-generation AI inference platform, the companies announced Thursday.

The collaboration will integrate FuriosaAI's Tensor Contraction Processor (TCP) architecture into a multi-die chiplet system designed for hyperscale AI infrastructure. 

The third-generation AI accelerator will use a 2-nanometer process compute die and incorporate High Bandwidth Memory (HBM4 and HBM4E).

Under the agreement, Broadcom will provide advanced packaging technology to combine multiple silicon dies into a single chip. 

The platform will also use Broadcom's AI networking and high-bandwidth Ethernet switch technologies to support rack-level networking within large-scale AI inference clusters.

The companies plan to begin sampling the accelerators in the first half of 2028. The hardware is designed to process workloads for large language models and agentic AI services.

The platform builds on the architecture of FuriosaAI's second-generation accelerator, the RNGD. Currently in mass production, the RNGD is a 180W PCIe AI accelerator manufactured on TSMC's 5-nanometer process and equipped with SK Hynix HBM3 memory. 

The RNGD system has completed verification testing with enterprise clients, including Samsung SDS and LG AI Research.

Charlie Kawwas, president of Broadcom's Semiconductor Solutions Group, said AI inference performance is increasingly dependent on data reuse and communication efficiency between servers and racks, rather than solely on computing power. 

He said the joint platform will combine FuriosaAI's TCP architecture with Broadcom's XPU technology, IP platform, and Ethernet scale-up networking to address bottlenecks in large-scale AI environments.

FuriosaAI Chief Executive June Paik said the integration of Broadcom's infrastructure technologies with FuriosaAI's hardware and software stack aims to optimize performance-per-watt metrics for hyperscale AI systems.